“Engineering Sustainable Semiconductor Solutions for our World.”
Although TFI is very cautious about projections we believe that our company will be very attractive to a major semiconductor industry player in 2 to 3 years after the 2nd stage of funding. This may take the form of an acquisition, merger, or IPO. The most likely acquirers will be Chinese and South Korean toolmakers who will be motivated in retaining market share and innovation advantages. A strong ROI for our investors is a very important component of our strategy.
Although several competitors are attempting to develop similar processes and equipment, TFI is the only company that could be market and manufacturing-ready in 2022 with its new generation of 3DIC processes and equipment, featuring International, U.S, and Korean patents to back it up.
Yes. TFI has created an efficient and working demo prototype that is customizable for the specific requirements and needs of each customer. Our future North American headquarters in Irvine, California will demonstrate those capabilities. Customers in several countries are awaiting the rollout of this new technology.
Currently, TFI provides CU (Copper) and Seed equipment. Future interconnects must have conformal step coverage, smooth surface morphology, and strong adhesion. Today we see that the Cu Barrier, Cu Seed, and Cu Fill are separated processes. TFI’s breakthrough technology is working to provide an "All-in-One System.”
For over thirty years the Physical Vapor Deposition sputtering (PVD) has been used for metallization deposits. This has technical limitations. It does not meet the required process performance for Through-Silicon Via (TSV) devices. These have a smaller footprint on a silicon wafer.
Currently, customers cannot remain competitive with the limitations of PVD. Our goal is to have TFI’s Wet Metal Deposition Process replace the old PVD tools.
TFI has ongoing demonstrations and reviews. We run wafer-level demos to confirm the process and its productivity for potential USA, Korean and European customers. These requests also extended to an LED device manufacturer from China. Early on we recognized that potential customers want an on-site demonstration of our process and to see if it applies to their production needs. This is done through the Joint Development Program (JDP). This is the standard business practice that device makers use when reviewing and adopting new processes and equipment.
There will be two manufacturing sites: An R&D and demonstration lab in Irvine, California for North American & European customers and one in South Korea for the Asia-Pacific market.
Once the fundraising goal has been met in the United States, we anticipate that the matching grant from the South Korean government to take 10 to 12 weeks.
TFI's process uses chemicals fully proven for safety and being non-toxic. Just as importantly, they can be diluted 100% without residue, dust, sludge deposits, or air contamination. Our clean technology exceeds current standards and fulfills our goal of a sustainable semiconductor solution. The State of California has already had discussions and reviews on fast-tracking permits and licenses for TFI.
Our new wet metal deposition technology deposits metal conduct interconnection in devices and chips using non-toxic chemical sources. Unlike conventional deposition methods using dry gas and solid material sources, ours is engineered to be a sustainable solution.
Several methods of "wet" metal deposition exist, depending on the kind of energy used to promote the reducing electrons to a level suitable for the reduction step. Among these "wet" methods, is the electroless or autocatalytic technique. This technique preparation is particularly well adapted for Three-Dimensional Integrated Circuits.
A three-dimensional integrated circuit (3D IC) is a metal-oxide-semiconductor integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, Through-Silicon Vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two-dimensional processes.*
In electronic engineering, a through-silicon via (TSV) is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. Compared to alternatives such as package-on-package, the interconnect and device density is substantially higher, and the length of the connections becomes shorter.*